1. Field of the Invention
The present invention relates to a timing controller and a liquid crystal display (LCD) device using the same, and more particularly, to a timing controller for receiving RGB data to output WRGB data, a driving method thereof, and an LCD device using the same.
2. Discussion of the Related Art
With the advancement of various portable electronic devices such as mobile phones, personal digital assistants (PDAs), and notebook computers, the demands for Flat Panel Display (FPD) devices applicable to the portable electronic devices are increasing.
LCD devices, plasma display panels (PDPs), field emission display (FED) devices, and light emitting display devices are considered FPD devices.
In such FPD devices, LCD devices are devices that display an image using the optical anisotropy of liquid crystal. Since the LCD devices have a thin thickness, a small size, and low power consumption and realize a high-quality, the LCD devices are widely used.
FIG. 1 is an exemplary diagram illustrating a communication method between an external memory 500 and a timing controller 40 applied to a related art LCD device. FIG. 2 is an exemplary diagram illustrating a data timing for transmitting and receiving WRGB data between the external memory 500 and the timing controller 40 applied to the related art LCD device.
The related art LCD device includes the timing controller 40, a source driver IC, a gate driver IC, and a panel. Generally, the timing controller 40 is mounted on a main board connected to a flexible printed circuit board (FPCB). In addition to the timing controller 40, various electronic components are mounted on the timing controller 40. The external memory 500, which temporarily stores data transmitted from the timing controller 40 and transmits the data to the timing controller 40, is also mounted on the main board.
Generally, the panel of the related art LCD device includes a plurality of red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels for realizing colors. To this end, input RGB data are inputted from an external system (for example, a television set) to the timing controller 40 of the related art LCD device.
An LCD device, having a WRGB pixel structure that includes both RGB sub-pixels having three primary colors and a white (W) sub-pixel transmitting white light, is recently developed for enhancing luminance of LCD devices.
The LCD device having the WRGB sub-pixel structure converts input RGB data, inputted from the external system, into digital WRGB data and converts the digital WRGB data into analog WRGB signals to output the WRGB signals through the panel. A function of converting the input RGB data into the WRGB data is performed by the timing controller 40.
In this process, the WRGB data is required to be temporarily stored in the external memory 500, in order for the timing controller 40 to convert the input RGB data into the WRGB data and output the WRGB data, and/or to perform a conversion operation (correction of image, removal of noise, compensation for image quality, etc.) on the WRGB data. That is, in order for the converted WRGB data from the timing controller 40 to be sequentially outputted to the source driver IC, the WRGB data needs to be temporarily stored in the external memory 500.
As described above, the external memory 500 is required to be driven at a high speed, for storing the WRGB data in the external memory 500. That is, a high-speed external memory clock (Ext Mem. CLK) is necessary for transmitting and receiving 16-bit data between the timing controller 40 and the external memory 500 according to the related LCD device. However, such a high-speed external memory clock exceeds the specification of the external memory 500 applied to the related art LCD device. Therefore, in the related art LCD device, the external memory 500 is unable to transmit and receive data with the high-speed external memory clock.
For example, as shown in FIG. 1, when each of RGB data applied to the related art LCD device is composed of 10 bits, and the external system and the timing controller 40 are connected with four ports, 120-bit RGB data are inputted to the timing controller 40. To this end, the external system and the timing controller 40 need a data clock driven at 40 MHz to 85 MHz. Then, the 10-bit data are transmitted from the external system to the timing controller 40 with one piece of data clock driven at 40 MHz to 85 MHz.
Since the WRGB data generated by the timing controller 40 are composed of a total of 40 bits (=10 bits×4), and the timing controller 40 and the external memory 500 communicate with each other through the four ports, 160-bit WRGB data are then transmitted and received between the timing controller 40 and the external memory 500.
In this case, since 16-bit data are transmitted and received between the timing controller 40 and the external memory 500, ten data clocks are necessary for transmitting and receiving the 160-bit WRGB data. The timing controller 40 and the external memory 500 transmit and receive data through two lines, and thus, five data clocks are actually required.
Therefore, as shown in FIG. 2, the external memory 500 is required to be driven at a frequency of 200 MHz (=40 MHz×5) to 425 MHz (=85 MHz×5) that enables transmission of the five data clocks.
However, the external memory 500 (for example, DDR2) instead uses a frequency of 400 MHz as a memory clock at present. For this reason, in the related art LCD device using the external memory 500, the WRGB data outputted from the timing controller 40 are not properly inputted to the external memory 500, or the WRGB data are not properly outputted from the external memory 500 to the timing controller 40, which is a limitation that needs to be addressed.
To provide an additional description, in the related art LCD device using the WRGB pixel structure, the input RGB data are converted into the WRGB data, which undergo a conversion operation using various algorithms, and are displayed as an image through the panel. In this case, an internal memory (for example, SRAM) included in the timing controller 40 and the external memory 500 (external frame memory) disposed outside the timing controller 40 are used. The internal memory is disposed at a front end of a memory control unit of the timing controller 40 communicating with the external memory 500, or the internal memory is disposed at a rear end of the memory control unit. However, when each of input RGB data is composed of 120 bits, it is unable to apply the 120-bit RGB data to the related art external memory 500 that transmits and receives 16-bit data. That is, since an external memory clock of 200 MHz to 425 MHz in the timing controller 40, which is used for receiving WRGB data into which input RGB data driven at 85 MHz have been converted, exceeds the specification (400 MHz) of the external memory 500, the timing controller 40 is unable to apply the data to the external memory 500.
Further the above-described limitations occur in different types of flat panel display devices using the timing controller 40 and the external memory 500, in addition to the LCD devices.
Moreover, the external memory 500 generally has a fixed frequency (400 MHz) and a data clock is variable. Therefore, if the design of the external memory 500 is changed to be driven at a different frequency each time the frequency of the external memory 500 needs to be changed because, as described above, the amount of data transmitted/received between the timing controller 40 and the external memory 500 is changed, or the data clock is changed, then the manufacturing cost of such flat panel display devices would increase inevitably.